Until recently, integrated circuit (IC) scaling has been enabled to a large extent by improvements in photolithography equipment resolution and overlay. The resolution capability of the photolithography equipment was such that random logical functions could be drawn with two-dimensional (2D) bent shapes, with few restrictions on shape dimensions or relationships between shapes.
Traditional 2D designs have layout shape edges which can fall on a very fine grid, such as on a 1 nm (nanometer) grid, by way of example. A direct writing tool using a raster pattern needs to write along the finest grid on each design/pattern layer of an integrated circuit device (sometimes called a mask layer) in order to correctly place all edges of the layout shapes. Also, 2D layout patterns need to be written completely in two directions, resulting in a large amount of data for each layer to be written. It is within this context that the present invention arises.